Display panel and liquid crystal display including signal lines

ABSTRACT

A liquid crystal display includes a plurality of signal lines. The signal lines are parallel to each other in a display area, the distances between the signal lines vary such that the signal lines are arranged like a fan in a fan-out area, and the signal lines are connected to a driving circuit in a connection area. Each signal line includes a single-layered portion and a double-layered portion located in the fan-out area, and the length of the single-layered portion of relatively longer signal line is relatively shorter.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a display panel including a pluralityof signal line, and particularly to a liquid crystal display including aplurality of lines having different length.

(b) Description of Related Art

A display device such as a liquid crystal display (LCD) or an organicelectroluminescence (EL) display includes a plurality of pixels as basicelements for displaying an image. Each pixel includes a switchingelement for independent operation.

The switching elements include a tri-terminal element including acontrol terminal, an input terminal, and an output terminal, which isturned on or off in response to a signal applied to the control terminaland selectively transmits a signal entering into the input terminal viathe output terminal. For this purpose, a plurality of signal lines forapplying the signals to the control terminals and the input terminals ofthe switching elements and a plurality of driving circuits for supplyingthe signals to the signal lines are provided at a display device.

The TFT array panel includes a plurality of scanning signal lines orgate lines for transmitting scanning signals, a plurality of imagesignal lines or data lines for transmitting image signals, a pluralityof TFTs connected to the gate lines and the data lines, a plurality ofpixel electrodes connected to the TFTs, a gate insulating layer coveringthe gate lines for insulation, and a passivation layer covering the TFTsand the data lines for insulation.

The TFT includes a gate electrode, which is a part of the gate line, asemiconductor layer for a channel, source and drain electrode, which areparts of the data line, a gate insulating layer, and a passivationlayer. The TFT is a switching element for transmitting or blocking theimage signal from the data line to the pixel electrode in response tothe scanning signal from the gate line.

The driving circuits are located near edges of the display device andconnected to end portions of the signal lines, which are clustered in asmall area (referred to as “connection area” hereinafter) for theconnection. On the contrary, the distances between the signal lines inan area (referred to as “display area”) including the pixels have avalue determined by the size of the pixels to have larger values thanthe distances between their end portions connected to the drivingcircuits. Accordingly, a plurality of fan-out areas in which thedistances between the signal lines gradually increase or decrease like afan are provided between the connection area and the display area.

Although the signal lines near the center of the fan-out area extendsstraight without curving, the signal lines closer to edges of thefan-out area have larger curving angles. This configuration of thefan-out area results in the difference in the length between the signallines such that the line length near the center of the fan-out area isshorter than the line length near the edges of the fan-out area. Thelength difference differentiates the resistances of the signal lines,which results in the deteriorated image quality.

In particular, since a liquid crystal display uses a voltage controlscheme which controls voltages applied to the pixels, the voltagedifference due to the resistance difference causes a severe problem inimage quality.

SUMMARY OF THE INVENTION

A motivation of the present invention is to reduce resistance differencedue to length difference of signal lines.

A display panel including a plurality of signal lines is provided. Eachsignal line includes a first portion and a second portion, and thedisplay panel includes a first area including the first portions of thesignal lines and a second area including the second portions of thesignal lines. The first portions of the signal lines have substantiallythe same length and the second portions of the signal lines havedifferent lengths. The second portion of each signal line includes athird portion and a fourth portion and the third and the fourth portioninclude at least one layer. The number of layers in the third portion issmaller than the number of layers in the fourth portion.

The length of the third portion of each signal line preferably dependson the entire length of the signal line. Preferably, the length of thethird portion of relatively longer signal line is relatively shorter,and in particular, the length of the third portion of each signal lineis inversely proportional to the entire length of the signal line.

It is preferable that each signal line further includes a fifth portionfor connection with outside, and the display panel further includes athird area including the fifth portions of the signal lines and locatedopposite the first area with respect to the second area.

The signal lines may be arranged like a fan in the second area, and thelength of the signal line closer to edges of the second area is longer.

The display panel may further include a driving circuit connected to thesignal lines in the third area and supplying signals to the signallines. The driving circuit is chip-mounted on the display panel ormounted on a separately provided printed circuit. The printed circuitincludes a plurality of conductive lines for electrical connectionbetween the driving circuit and an external device, and the conductivelines are connected to the signal lines in the third area.

Preferably, the third portion of each signal line has a single-layeredstructure while the fourth portion of each signal line has adouble-layered structure.

A display panel including a plurality of signal lines is provided, thedisplay panel includes: a first area where distances between the signallines are substantially the same, and a second area where distancesbetween the signal lines vary. Each signal line includes a first portionand a second portion, the first and the second portion of each signalsline are located in the second area and include at least one layer, andthe number of layers in the first portion is smaller than the number oflayers in the second portion.

It is preferable that the lengths of the signal lines in the second areaare different, the length of the first portion of relatively longersignal line is relatively shorter, and the signal lines are arrangedlike a fan in the second area.

Preferably, the display panel further includes a third area locatedopposite the first area with respect to the second area, and thedistances between the signal lines in the third area are shorter thanthe distances between the signal lines in the first area.

The display panel may further include a driving circuit connected to thesignal lines in the third area and supplying signals to the signallines.

A liquid crystal display according to an embodiment of the presentinvention includes a display area, first and second fan-out areas, andfirst and second connection areas. The liquid crystal display includes:an insulating substrate; a plurality of gate lines formed on thesubstrate, each gate line including a connecting portion; a plurality ofdata lines insulated from the gate lines and intersecting the gate linesin the display area, each data line including a connecting portion; agate driving circuit connected to the connecting portions of the gatelines in the first connection areas; and a data driving circuitconnected to the connecting portions of the data lines in the secondconnection areas. Each gate line or data line include a lower portionincluding at least one layer and located in the first or the secondfan-out area, and the number of layers in the lower portion is smallerthan the number of layers in other portions.

It is preferable that the length of the lower portion of relativelylonger gate line or data line is relatively shorter, and the length ofthe lower portion closer to a center of the driving circuits is longer.

Preferably, the liquid crystal display further includes a plurality ofthin film transistors connected to the gate lines and the data lines anda plurality of pixel electrodes connected to the thin film transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of the present invention will become moreapparent by describing preferred embodiments thereof in detail withreference to the accompanying drawings in which:

FIG. 1 is a schematic layout view of an LCD according to an embodimentof the present invention;

FIG. 2 is a schematic layout view of an LCD according to anotherembodiment of the present invention;

FIG. 3 is a schematic perspective view of an LCD according to anotherembodiment of the present invention;

FIG. 4 is an enlarged layout view of a fan-out area shown in FIGS. 1 and2;

FIG. 5 is a sectional view of the fan-out area shown in FIG. 4 takenalong the line V-V′;

FIG. 6 is a sectional view of the fan-out area shown in FIG. 4 takenalong the line VI-VI′; and

FIG. 7 is a graph showing resistances of signal lines in a fan-out areaof a panel according to an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the present invention are shown. The present invention may, however,be embodied in many different forms and should not be construed aslimited to the embodiments set forth herein.

In the drawings, the thickness of layers and regions are exaggerated forclarity. Like numerals refer to like elements throughout. It will beunderstood that when an element such as a layer, region, panel orsubstrate is referred to as being “on” another element, it can bedirectly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” another element, there are no intervening elements present.

Now, display panels and liquid crystal displays (LCDs) according toembodiments of the present invention will be described in detail withreference to the drawings.

FIG. 1 is a schematic layout view of an LCD according to an embodimentof the present invention, FIG. 2 is a schematic layout view of an LCDaccording to another embodiment of the present invention, and FIG. 3 isa schematic perspective view of an LCD according to another embodimentof the present invention.

Referring to FIG. 1, an LCD according to an embodiment of the presentinvention includes a liquid crystal panel assembly 300, a plurality ofgate flexible printed circuit (FPC) films 410 and a plurality of dataFPC films 510 attached to the panel assembly 300, and a printed circuitboard (PCB) 550 attached to the data FPC film 510.

Referring to FIG. 3, the panel assembly 300 includes a lower panel 1 andan upper panel 2 facing each other and a liquid crystal layer 3interposed between the two panels 1 and 2.

The upper panel 2 includes a black matrix 220 having a plurality ofapertures arranged in a matrix, a plurality of primary color filters 230such as red, green, and blue color filters disposed in respectiveapertures in the black matrix 220, and a common electrode 270 formed onan entire surface of the upper panel. These elements such as the blackmatrix 220, the color filters 230, and the common electrode 270 may beprovided on the lower panel 1.

The lower panel 1 includes a plurality of pixel electrodes 190 arrangedin a matrix, a plurality of switching elements Q connected to the pixelelectrodes 190, a plurality of gate lines 121 connected to the switchingelements Q and transmitting gate signals (also referred to as “scanningsignals”), and a plurality of data lines 171 connected to the switchingelements Q and transmitting data signals.

The pixel electrodes 190 face the apertures of the black matrix 220 andare preferably made of a transparent conductive material such as indiumtin oxide (ITO) and indium zinc oxide (IZO) or of a reflective metal.

The switching elements Q includes three-terminal thin film transistors(TFTs), each switching element Q having control and input terminalsrespectively connected to the gate line 121 and the data line 171 and anoutput terminal connected to the pixel electrode 190 such that theswitching element Q selectively transmits the data signals from the datalines 171 responsive to the gate signals from the gate lines 121.

Referring back to FIG. 1, a plurality of gate driver integrated circuits(ICs) 410 and a plurality of data driver ICs are chip-mounted on thegate FPC films 410 and the data FPC films 510, respectively. A pluralityof leads 420 and 520 for electrical connection to an external device areformed on the FPC films 410 and 510, respectively.

Various circuit elements for driving and controlling the panel assembly300 are provided on the PCB 550. The circuit elements are connected tothe data driver ICs 540 via signal lines (not shown) provided on the PCB550 and the leads 520 on the data FPC films 510. The electricalconnection between the gate driver ICs 440 and the PCB 550 is made bysignal lines (not shown) separately provided on the data PCB 550 and thelower panel 1 and the leads 420 on the gate FPC films 410.

Another embodiment shown in FIG. 2 mounts the driver ICs 440 and 550directly on the lower panel 1 of the panel assembly 300, and the gateFPC film is not required. The PCB 550 and the data FPC film 510 are notshown in FIG. 2 for descriptive convenience.

According to another embodiment, an additional PCB (not shown) isattached to the gate FPC films 410, and some circuit elements of the PCB550 are provided on the additional PCB.

According to an embodiment of the present invention, the driver ICs 440and/or 540 are integrated into the lower panel 1, instead of beingchip-mounted.

Referring to FIGS. 1 and 2, the lower panel 1 is divided into a displayarea D including the array of the pixel electrodes 190, and a peripheralarea located outside the display area D and including the connectionsbetween the display signal lines 121 and 171 and the FPC films 410 and510 (as shown in FIG. 1) or the driving ICs 440 and 540 (as shown inFIG. 2).

The display signal lines 121 or 171 are connected to the pixelelectrodes 190 through the switching elements Q in the display area andextend substantially parallel to each other. The signal lines 121 and171 have one ends connected to the FPC films 410 and 510 or the driverICs 440 and 540. As shown in FIG. 1, the distance between the leads 420of the FPC films 410 and 510 for the connection between the driver ICs440 and 540 and the display signal lines 121 and 171 is smaller than thedistance between the signal lines 121 or 171 in the display area D.Similarly, the distance between output terminals of the driver ICs 440and 540 to be connected to the display signal lines 121 and 171 issmaller, as shown in FIG. 2, than the distance between the signal lines121 or 171 in the display area D. Accordingly, there are a plurality offan-out areas where the distance between the signal lines 121 or 171varies such that the signal lines 121 or 171 are arranged like a fan.

Now, a fan-out area of a panel according to an embodiment of the presentinvention is described in detail with reference to FIGS. 4-6.

FIG. 4 is an enlarged layout view of a fan-out area shown in FIGS. 1 and2, FIG. 5 is a sectional view of the fan-out area shown in FIG. 4 takenalong the line V-V′, and FIG. 6 is a sectional view of the fan-out areashown in FIG. 4 taken along the line VI-VI′.

As shown in FIG. 4, signal lines SL₁-SL_(n) such as gate lines 121 ordata lines 171 are arranged like a fan in a fan-out area located betweena display area D and a connection area CA. The connection area CA is anarea where end portions of the signal lines SL₁-SL_(n) are connected toFPC films 410 and 510 or driver ICs 440 and 540. The signal line such asSL_(n/2) near a center C goes straight without curving. The signallines, as they are closer to edges E of the fan-out area F, show largercurving angles, and the signal lines SL₁ and SL_(n) closest to the edgesE have the largest curving angles. Therefore, the length of portions ofthe signal lines SL₁-SL_(n) in the fan-out area F and the length of thesignal lines SL₁-SL_(n) becomes longer as it goes to the edges F fromthe center C.

Each of the display signal lines SL₁-SL_(n) includes at least one of alower layer N₁-N_(n) and an upper layer M₁-M_(n), which are sequentiallydeposited on a substrate 40 and made of conductive material such asmetal. The two layers N₁-N_(n) and M₁-M_(n) may have differentresistivity. It is preferable that one of the two layers N₁-N_(n) andM₁-M_(n) are made of low resistivity metal such as Al, Al alloy, Ag andAg alloy, and the other of the two layers N₁-N_(n) and M₁-M_(n) are madeof Cr, Ti, Ta, Mo or their alloys such as MoW alloy having goodphysical, chemical and electrical contact characteristics with othermaterials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

Referring to FIGS. 5 and 6, each signal line SL₁-SL_(n) include asingle-layered portion L₁-L_(n) which extends to the connection area CA.The length of the single-layered portions L₁-L_(n) of the signal linesSL₁-SL_(n) becomes shorter as the length of the corresponding signallines SL₁-SL_(n) becomes longer. For example, the length of thesingle-layered portion L₁-L_(n) is inverse proportional to the length ofthe corresponding signal line SL₁-SL_(n).

As a result, the resistance of the signal lines SL₁-SL_(n) in thefan-out area F is uniform. That is, the resistance difference of thelength of portions in the fan-out area F or of the entire length of thesignal lines SL₁-SL_(n) is compensated by making the single-layeredportions L₁-L_(n) of longer signal lines SL₁-SL_(n) shorter, whilemaking those of shorter signal lines SL₁-SL_(n) longer since thesingle-layered portion L₁-L_(n) has larger resistance than otherportions including two layers N₁-N_(n) and M₁-M_(n) electricallyconnected in parallel.

For example, it is assumed that the length of a portion of a signal lineSL_(i) in a fan-out area F and the length of the single-layered portionL_(i) of the signal line SL_(i) are indicated by t_(i) and s_(i),respectively, the resistivities of the lower layer N_(i) and the upperlayer M_(i) are indicated by ρ_(N) and ρ_(M), respectively, and theareas of the sections of the lower layer N_(i) and the upper layer M_(i)are equal and indicated by A.

The resistance R_(i)(single) of the single-layered portion L_(i) of thesignal layer SL_(i) is given by, $\begin{matrix}{{R_{i}({single})} = {\rho_{N}{\frac{s_{i}}{A}.}}} & (1)\end{matrix}$

The resistance R_(i)(double) of the remaining double-layered portion ofthe signal layer SL_(i), which equals to the combined resistance of theresistance R_(i)(lower) of the lower layer N_(i) and the resistanceR_(i)(upper) of the upper layer M_(i) connected in parallel, is givenby, $\begin{matrix}{{R_{i}({double})} = {\frac{1}{{1/{R_{i}({lower})}} + {1/{R_{i}({upper})}}} = {\frac{\rho_{N}\rho_{M}}{\rho_{N} + \rho_{M}}{\frac{t_{i} - s_{i}}{A}.}}}} & (2)\end{matrix}$

Accordingly, the total resistance R_(i) of the portion of the signalline SL_(i) in the fan-out area F is obtained such that: $\begin{matrix}{R_{i} = {{{R_{i}({single})} + {R_{i}({double})}} = {{\rho_{N}\frac{s_{i}}{A}} + {\frac{\rho_{N}\rho_{M}}{\rho_{N} + \rho_{M}}{\frac{t_{i} - s_{i}}{A}.}}}}} & (3)\end{matrix}$

Since the resistances of the portions of the signal lines SL₁-SL_(n) inthe fan-out area F are preferably equal to each other, the lengthss₁-s_(n) of the single-layered portion L₁-L_(n) of the signal linesSL₁-SL_(n) are adjusted such that the resistances R₁-R_(n) of all thesignal lines given by Equation 3 are the same.

FIG. 7 is a graph showing resistances of signal lines in a fan-out areaof a display panel having a signal line configuration. The line shown inFIG. 2 illustrates that the resistances of all the signal lines are thesame. The term “substantially the same” means “the same” if theresistance deviation due to device error of a manufacturing device formanufacturing the signal lines SL₁-SL_(n) and or operation error of themanufacturing device is ignored.

As described above, the embodiments of the present invention providedual-layered signal lines for reducing the resistance difference due tothe length difference in a fan-out area, thereby effectively removingimage deterioration due to the resistance difference.

Although the embodiments focus on LCDs, the present invention is alsoapplicable to any display devices having fan-out areas.

While the present invention has been described in detail with referenceto the preferred embodiments, it is to be understood that the inventionis not limited to the disclosed embodiments, but, on the contrary, isintended to cover various modifications and equivalent arrangementsincluded within the sprit and scope of the appended claims.

1. A display panel including a plurality of signal lines, each signalline including a first portion and a second portion, the display panelcomprising: a first area including the first portions of the signallines; and a second area including the second portions of the signallines, where the first portions of the signal lines have substantiallythe same length, the second portions of the signal lines have differentlengths, the second portion of each signal line includes a third portionand a fourth portion including at least one layer, and the number oflayers in the third portion is smaller than the number of layers in thefourth portion.
 2. The display panel of claim 1, wherein the length ofthe third portion of each signal line depends on the entire length ofthe signal line.
 3. The display panel of claim 2, wherein the length ofthe third portion of relatively longer signal line is relativelyshorter.
 4. The display panel of claim 3, wherein the length of thethird portion of each signal line is inversely proportional to theentire length of the signal line.
 5. The display panel of claim 4,wherein each signal line further comprises a fifth portion forconnection with outside, and the display panel further comprises a thirdarea including the fifth portions of the signal lines and locatedopposite the first area with respect to the second area.
 6. The displaypanel of claim 5, wherein the signal lines are arranged like a fan inthe second area.
 7. The display panel of claim 6, wherein the length ofthe signal line closer to edges of the second area is longer.
 8. Thedisplay panel of claim 5, further comprising a driving circuit connectedto the signal lines in the third area and supplying signals to thesignal lines.
 9. The display panel of claim 8, wherein the drivingcircuit is chip-mounted on the display panel.
 10. The display panel ofclaim 8, further comprising a printed circuit mounting the drivingcircuit and including a plurality of conductive lines for electricalconnection between the driving circuit and an external device, theconductive lines connected to the signal lines in the third area. 11.The display panel of claim 2, wherein the third portion of each signalline has a single-layered structure and the fourth portion of eachsignal line has a double-layered structure.
 12. A display panelincluding a plurality of signal lines, the display panel comprising: afirst area where distances between the signal lines are substantiallythe same, and a second area where distances between the signal linesvary, where each signal line includes a first portion and a secondportion, the first and the second portion of each signals line arelocated in the second area and include at least one layer, and thenumber of layers in the first portion is smaller than the number oflayers in the second portion.
 13. The display panel of claim 12, whereinthe lengths of the signal lines in the second area are different, andthe length of the first portion of relatively longer signal line isrelatively shorter.
 14. The display panel of claim 13, furthercomprising a third area located opposite the first area with respect tothe second area, the distances between the signal lines in the thirdarea being shorter than the distances between the signal lines in thefirst area.
 15. The display panel of claim 14, wherein the signal linesare arranged like a fan in the second area.
 16. The display panel ofclaim 15, further comprising a driving circuit connected to the signallines in the third area and supplying signals to the signal lines.
 17. Aliquid crystal display including a display area, first and secondfan-out areas, and first and second connection areas, the liquid crystaldisplay comprising: an insulating substrate; a plurality of gate linesformed on the substrate, each gate line including a connecting portion;a plurality of data lines insulated from the gate lines and intersectingthe gate lines in the display area, each data line including aconnecting portion; a gate driving circuit connected to the connectingportions of the gate lines in the first connection areas; and a datadriving circuit connected to the connecting portions of the data linesin the second connection areas, wherein each gate line or data lineinclude a lower portion including at least one layer and located in thefirst or the second fan-out area, and the number of layers in the lowerportion is smaller than the number of layers in other portions.
 18. Theliquid crystal display of claim 17, wherein the length of the lowerportion of relatively longer gate line or data line is relativelyshorter.
 19. The liquid crystal display of claim 18, wherein the lengthof the lower portion closer to a center of the driving circuits islonger.
 20. The liquid crystal display of claim 17, further comprising:a plurality of thin film transistors connected to the gate lines and thedata lines; and a plurality of pixel electrodes connected to the thinfilm transistors.